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EC Modeling of faults. Test generation for combinational logic circuits :conventional methods path sesitisation,Boolean difference , Random testing, transition count testing and signature analysis. Fault Tolerant Design-II: Time redundancy, software redundancy, fail-soft operation, examples of practical fault tolerant systems, introduction to fault tolerant design of VLSI chips.
Testing and testable design of high-density random-access memories
Self checking circuits: Design of totally self checking checkers, checkers using m-out of a codes, Berger codes and low cost residue code, self-checking sequential machines, partially self-checking circuits. Electronics and Communications Engineering Books.
Mazumder Pinaki. Testing and Testable Design of High-Density Random-Access Memories deals with the study of fault modeling, testing and testable design of semiconductor random-access memories.
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It is written primarily for the practising design engineer and the manufacturer of random-access memories RAMs of the modern age. It provides useful exposure to state-of-the-art testing schemes and testable design approaches for RAMs.
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It is also useful as a supplementary text for undergraduate courses on testing and testability of RAMs. These new techniques are being used for increasing the memory testability and for lowering the cost of test equipment.
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